The present invention relates to integrated bidirectional transceiver (transmitter and receiver) circuits for use in data transmission systems and, more particularly, to integrated interface circuits for transmitting/receiving data items serially to/from a data bus connected to a data transmission system.
The present invention further relates to integrated interface circuits for interfacing signal buses and devices connected thereto in digital data processing systems and, more particularly, to interface circuits for interfacing general-purpose serial buses and devices connected thereto.
In the field of personal computers (PCs) and accessories, there have been rapid performance improvements in processors and memories. For example, processors have progressed from Pentium to Pentium III, and DRAM speed and sizes continually improved through the 1990""s. However, peripherals such as keyboards, mouses, monitors, printers, speakers, microphones, and telephone/fax modems, remained largely unchanged during this period.
With the advent of new advanced general-purpose buses, such as USB (Universal Serial Bus), FW (Fire Wire; sometimes called IEEE1394), FC (Fiber Channel), and SSA (Serial Storage Architecture), major changes to almost every peripheral for personal computers or workstations are imminent. The advanced serial buses are described, for example, in U.S. Pat. Nos. 5,523,610; 5,621,901; and 5,579,336.
Among the above advanced buses, USB promises to become a next generation computer peripheral interface, along with FW suitable for multimedia environments. USB brings Plug-and-Play technology to the external input and output devices found on today""s high-performance PCs or workstations. USB has three major advanced features as follows: (1) ease of use through hot plugging and automatic configuration, (2) standardized connection points and simplified connector design, and (3) simple expansion through the use of a tiered-star hub topology.
Older computer connections like RS232 COMx serial ports and parallel printer LPTx ports can only be connected to a single device at a time. In contrast, USB allows simultaneously attaching and using of multiple devices on the same bus. USB also allows these devices to be attached and removed while the computer system is running and without requiring a reboot to use a newly attached device. USB allows virtually unlimited PC expansion xe2x80x9coutside the boxxe2x80x9d. Once PC users open the box to install expansion cards, they are faced with a complex and bewildering collection of dip switches, circuit boards, jumper cables, peripheral drivers, IRQ settings, DMA channels and I/O addresses that must be configuredxe2x80x94and often reconfigured. To make matters worse, expanding PC functionality often brought increased system crashes, thereby costing work productivity, time, and effort to the frustrated users. For any PC user who has ever guessed about which port to select, or fretted over a dip switch, USB is the solution. With USB, PC users no longer need to worry about selecting the right serial port, installing expansion cards, or the technical headaches of dip switches, jumpers, software drivers, IRQ settings, DMA channels and I/O addresses.
The USB specification (Reversion 1.0 Jan. 15, 1996) defines four transfer types to enable a variety of peripherals: Control, Isochronous, Interrupt and Bulk. Every peripheral must support Control transfers for configuration, command, and status information flows. Isochronous transfers provide guaranteed bus access, constant data rate and error tolerance for devices such as computer-telephone integration, audio systems, and multimedia game equipment. Interrupt transfers were designed to support human input devices such as joysticks, mice and keyboards that communicate the occasional bursts of data, but with bounded service periods. Bulk transfers enable devices like printers, scanners, and digital cameras to communicate a larger amount of data to the PC as bus bandwidth becomes available.
The USB topology has three elements that work together to enable the four different transfer types: Host, Hub, and Function. Within a USB system, the host controls the flow of data and control information over the bus. This host capability is normally found on the PC motherboard. Functions provide capabilities to the host system. These functions can include typical PC activities such as keyboard or joystick input and monitor controls, or more advanced activities like digital telephony and image transfer. Finally, hubs provide an expansion point for USB by supplying a connection to other USB functions. USB hubs play an integral role in expanding the world of the PC user. With device connections furnished by embedded hubs in keyboards, monitors, printers, and other devices, attaching or removing a new peripheral is as simple as reaching for the plug.
For even simpler connectivity, the USB cable consists of only four wires: Vbus, DP(or D+), DM (or Dxe2x88x92), and GND. A single standardized upstream connector type further increases the ease-of-use of USB peripherals. The data is differentially driven over DP and DM at a bit rate of 12 Mbps for full-speed signaling, or a rate of 1.5 Mbps for the USB low-speed signaling mode. The data transfer rate of 12 Mbps supports a wide variety of peripherals, from modems, printers, microphones, and speakers to graphics tablets, game controls,joysticks, scanners, monitors and digital cameras. The low-speed 1.5 Mbps option supports low-end, low-speed devices such as keyboards and mice for further cost reduction. Also, since USB distributes power (Vbus), many peripheral products (low-power devices) no longer require.separate power supplies.
As discussed above, since USB does not require the investment in expansion cards, the net cost of implementing new peripheral products can be substantially lower. Also, the universal compatibility of USB eliminates much of the cost of testing and validation of varying PC-peripheral-software combinations, while accelerating time-to-market. Thus, USB, featuring the above-described levels of throughput and expanded connectivity sites, could even bring about many new peripherals for the next generation of entertainment and productivity applications.
It is an object of the present invention to provide bidirectional serial data transceiver circuits for data transmission systems.
It is another object of the present invention to provide integrated serial bus interface circuits for transmitting/receiving data items serially to/from a data bus connected to a data transmission system.
It is still another object of the present invention to provide integrated serial bus interface circuits for interfacing serial signal bus cables and devices connected there to in digital data processing systems.
It is still another object of the present invention to provide serial bus interface circuits for interfacing general-purpose serial bus cables and devices connected thereto.
It is yet another object of the present invention to provide low-speed interface circuits for USB (universal serial bus), having simple architectures and are implemented on a single chip.
These and other objects, features and advantages of the present invention are provided by an integrated bus interface circuit for a computer system, which provides communication between a serial bus such as an USB cable and a function device such as a computer keyboard or mouse. An interface circuit according to the present invention includes a voltage regulator, a bidirectional serial data transceiver, a serial interface engine, and a device controller. The voltage regulator supplies a first power supply voltage (e.g., 3.3 volts) in a first voltage range by using a second power supply voltage (e.g., 5 volts) in a second voltage range. The transceiver converts a plurality of first signals of a bus-specific format (e.g., 3.3V modulated format) into a plurality of second signals of an interface-specific format (e.g., 5V modulated format), and conversely, by using the first and second power supply voltages. The serial interface engine performs an interface between the second signals and a plurality of third binary data signal of a device-specific format (e.g., 5V binary format). The device controller controls the function device in response to the third signals. The transceiver includes a transmitter for generating the bus-specific signals, a receiver for generating the interface-specific signals and a control logic controls the operations of the transmitter and receiver in response to a Tx/Rx select signal from the serial interface engine.
In a bus interface circuit according to the invention, the transmitter is responsive to a first encoded input data signal (e.g., NRZI) of the interface-specific format and a data end signal (e.g., EOP) to indicate an end of the first encoded input data signal from the interface engine which are of the interface-specific format, and provides a first and second encoded output data signals (e.g., DM and DP) of the bus-specific format to the serial bus. The receiver generates a plurality of encoded output data signals (e.g., RXDM, RXD and RXDP) of the interface-specific format in response to a couple of encoded input data signals (e.g., DM and DP) of the bus-specific format from the serial bus, so as to provide the encoded output data signals to the serial interface engine. The control logic selectively activates either of the transmitter and the receiver in response to a Tx/Rx select signal (e.g., SEL) from the serial interface engine. One of the third to fifth encoded output data signals is a differential signal of the other ones. The voltage regulator, transceiver, serial interface engine, and device controller are preferably implemented on a single semiconductor chip.
In the bus interface circuit, the integrated receiver includes a differential amplifier, two level shifters, three schmitt triggers, and an output drive logic. The differential amplifier amplifies a voltage difference between the first and second input data signals so as to generate a differential signal which swing in the same range as the data signals (e.g., DM and DP). The first level shifter shifts the swing voltage levels of the differential signal so as to generate a level-shifted differential signal as a first output data signal (RXD). The first schmitt trigger generates an output signal which exhibits a hysteresis in response to the swing of the first input data signal. The second level shifter which shifts the swing voltage levels of the output signal of the first schmitt trigger so as to generate a first level-shifted output data signal. The second schmitt trigger generates an output signal with a hysteresis in response to the swing of the second input data signal. The third level shifter shifts the swing voltage levels of the output signal of the second schmitt trigger so as to generate a second level-shifted output data signal. The output drive logic generates a second and third output data signals (e.g., RXDP and RXDM) in response to the enable signal and the first and second level-shifted output data signals. In this receiver circuit, the second and third output data signals are driven to a first data state when the input data signals both are in a first logic state and the enable signal is inactivated; to a second data state when the first input data signal is in a second logic state, the second input data signal in the second logic state and the enable signal is activated; and to a third data state when the first input data signal is in the first logic state, the second input data signal is in the second logic state and the enable signal is activated, respectively.
In the bus interface circuit, the transmitter comprises a first circuit responsive to a plurality of externally applied input signals and generates a plurality of state control signals (e.g., FNI, FNI#, PEN_DM, NENL_DM, PEN_DP, NENL_DP) to determine when the first and second data signals are driven to their predetermined data states, a second circuit which is responsive to the state control signals and generates a plurality of slope control signals (e.g., PBIAS, HVDD and NBIAS) to control edge rates of the data signals, a third circuit which is responsive to the state and slope control signals and generates the first data signal (DM) to be transmitted onto a first data line, and a fourth circuit which is responsive to the state and slope control signals and generates the second data signal (DP) to be transmitted onto a second data line. In the transmitter, the input signals comprises an encoded data signal (e.g., NRZI), a data end signal (e.g., EOP) to indicate an end of the encoded data signal, and an output enable signal (e.g., OE#). Also, in the transmitter, the first and second transmitted data signals (DM and DP) are driven to a first data state (e.g., Single Ended Zero state) when the data end and output enable signals are activated; to a second data state (e.g., Differential zero state) when the encoded data signal is in a first logic state, the data end signal is inactivated and the output enable signal is activated; and to a third data state (e.g., Differential one state) when the encoded data signal is in a second logic state, the data end signal is inactivated and the output enable signal is activated, respectively. When the output enable signal is inactivated, the first and second transmitted data signals (DM, DP) are driven to a high impedance state.
The transmitter of the present invention is implemented with no more than two operational amplifiers and their respective output drivers, providing increased integration for the bus interface chip, and improved internal capacitance facilitating stable output characteristics even with large variances in the load.